The present invention relates to a non-volatile memory, and more particularly, to a method of performing an erase-verify operation on a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure.
Non-volatile memory devices have been developed by the semiconductor integrated circuit industry for various applications such as computers and digital communications. A variety of non-volatile memory devices with oxide-nitride-oxide (ONO) structures have been developed. An example of a typical non-volatile memory cell with an ONO structure comprises a semiconductor substrate with source and drain regions, a channel region which is formed close to the surface of the semiconductor substrate between the source and the drain when electrical conduction occurs between the source and the drain, an oxide-nitride-oxide (ONO) film on top of the substrate surface between the source and the drain, and a gate on top of the ONO film. The ONO film comprises three layers including a first oxide layer on top of the substrate surface between the source and the drain, a nitride layer on top of the first oxide layer, and a second oxide layer on top of the nitride layer. The nitride layer in the ONO film is capable of trapping electrons which are generated in the channel region of the semiconductor substrate during a programming operation.
The conventional non-volatile memory cell with a typical ONO structure is programmed by generating hot electrons in the vicinity of the drain region in the substrate and injecting the hot electrons into the ONO film. More specifically, the hot electrons are trapped in a portion of the nitride layer close to the drain of the non-volatile memory cell. Because the nitride layer is an insulator, the hot electrons tend to remain in the portion of the nitride layer close to the drain without dispersing into other portions such as the center of the nitride layer.
The presence of the trapped hot electrons in the portion of the nitride layer adjacent the drain signifies that at least the drain side of the non-volatile memory cell is xe2x80x9cprogrammedxe2x80x9d. The non-volatile memory cell with a typical ONO structure may be programmed by applying high positive voltages to the gate and the drain and grounding the source of the non-volatile memory cell to inject hot electrons into the portion of the nitride layer adjacent the drain. This technique is also called channel hot electron programming.
FIG. 1 shows a cross-sectional view of a non-volatile memory cell 2 which comprises a substrate 4, an oxide-nitride-oxide (ONO) film 6 comprising a first oxide layer 8 on top of the substrate 4, a nitride layer 10 of top of the first oxide layer 8, and a second oxide layer 12 on top of the nitride layer 10. A polysilicon gate 14 is provided on top of the second outside layer 12. Portions of the substrate 4 are doped with a group V element, such as arsenic, to form a source region 16 and a drain region 18. The source and drain regions 16 and 18 may be produced by implanting arsenic into the substrate 4 to a depth in the range of about 300 xc3x85 to about 600 xc3x85. The ONO film 6 is positioned on top of a surface portion 20 of the substrate 4 between the source 16 and the drain 18.
The first oxide layer 8, which is also called a tunnel oxide layer, is positioned directly on top of the surface portion 20 of the substrate 4 between the source 16 and the drain 18. When conduction occurs between the source 16 and the drain 18, a channel is formed in the substrate 4 close to the surface 20 between the source 16 and the drain 18. The first oxide layer 8 may have a thickness on the order of about 75 xc3x85.
The nitride layer 10, which is positioned on top of the first nitride layer 8, is capable of trapping hot electrons which are generated in the channel and injected into a portion 34 of the nitride layer 10 close to the drain region 18 during a typical programming operation. The nitride layer 10 may have a thickness on the order of about 75 xc3x85. The second oxide layer 12, which is positioned on top of the nitride layer 10, has a thickness typically on the order of about 100 xc3x85. The gate 14, which is positioned on top of the second oxide layer 12, may be a conventional polysilicon gate which serves as a control gate for the non-volatile memory cell. The ONO film 6, which comprises the first oxide layer 8, the second oxide layer 12 and the nitride layer 10 sandwiched between the first and second oxide layers 8 and 12, may be fabricated by using conventional techniques known to a person skilled in the art.
FIG. 1 further shows portions of cross-sectional views of additional memory cells 22 and 24 adjacent the memory cell 2 in a non-volatile memory array. The nonvolatile memory cells 22 and 24 each have a device structure identical to the non-volatile memory cell 2 described above. Furthermore, two adjacent nonvolatile memory cells share a common arsenic-doped region which serves both as the drain for one of the cells and as the source for the other cell. For example, the arsenic-doped region 16, which serves as the source for the non-volatile memory cell 2, also serves as the drain for the non-volatile memory cell 22. Similarly, the arsenic-doped region 18, which serves as the drain for the non-volatile memory cell 2, also serves as the source for the non-volatile memory cell 24.
FIG. 1 shows a typical electron charge distribution in the substrate 4 after a typical programming operation in which channel hot electrons are generated in the substrate 4 and then trapped in the nitride layer 10. Such a programming operation is also called channel hot electron programming. After the non-volatile memory cell 2 is programmed, negative charge is formed in the portion of the substrate 4 beneath the substrate surface 20 between the source 16 and the drain 18. Electrons are trapped in this substrate region during the channel hot electron programming operation with an electron charge distribution in dependence upon the gate and drain voltages applied to the non-volatile memory cell 2 during the programming operation and the doping profiles for the source region 16 and the drain region 18.
More specifically, FIG. 1 shows an example of a typical electron charge distribution 26 in the portion of the substrate 4 between the source 16 and the drain 18 of the non-volatile memory cell 2 in which both the drain side and the source side are programmed. The negative charge in the substrate 4 is relatively concentrated in a first region 28 adjacent the source 16 and in a second region 30 adjacent the drain 18 after a typical channel hot electron programming operation. Furthermore, hot electrons are injected into the nitride layer 10 of the ONO film 6 during the programming operation.
Since the nitride layer 10 is an insulation layer, hot electrons which are trapped in the nitride layer 10 tend to remain localized within certain regions of the nitride layer 10 without spreading or dispersing into other regions of the nitride layer 10. In the example shown in FIG. 1 in which both the drain side and the source side are programmed, hot electrons 32 are trapped in a first portion 34 of the nitride layer 10 adjacent the drain 18 and a second portion 36 of the nitride layer 10 adjacent the source 16. Furthermore, as shown in FIG. 1, the center of the nitride layer 10 tends to be free of hot electrons, and the electron charge distribution in the substrate 4 tends to be minimal in the center region between the source 16 and the drain 18.
Depending upon the manner in which the nonvolatile memory cell 2 is programmed, electron charge distributions in the substrate 4 and the nitride layer 10 may be different from those shown in FIG. 1. For example, if only the drain side of the non-volatile memory cell 2 is programmed with hot electrons, only the portion 34 of the nitride layer 10 adjacent the drain 18 has a concentration of trapped hot electrons after the programming operation. Instead of the electron charge distribution 26 in the substrate 4 as shown in FIG. 1, the electrons in the substrate 4 would be concentrated in the substrate region 30 closer to the drain 18 beneath the portion 34 of the nitride layer 10 in which the hot electrons were trapped during the programming operation.
After the non-volatile memory cell is programmed, a conventional reading operation may be performed on the non-volatile memory cell by applying positive voltages to the drain and the gate and grounding the source of the non-volatile memory cell. For a conventional non-volatile memory cell with a typical ONO structure, the gate and drain voltages for the reading operation are respectively less than the typical gate and drain voltages for the channel hot electron programming operation. However, a sufficiently high drain voltage is typically applied to the drain of the non-volatile memory cell during the reading operation to cause deep saturation of charge in a region of the substrate adjacent the drain region and beneath the portion of the nitride layer in which the hot electrons accumulated during the programming operation. For example, a high drain voltage of at least 1.6 V is typically applied to the drain of a typical ONO-based non-volatile memory cell during the reading operation to achieve deep saturation of charge in the substrate region beneath the portion of the nitride layer in which the hot electrons were trapped during the programming operation.
FIG. 2 shows typical charge distributions during a typical reading operation in which the trapped hot electrons 32 in the portion 34 of the nitride layer 10 adjacent the drain region 18 are sensed after the drain side of the non-volatile memory cell 2 is programmed. In a typical reading operation, a high drain bias voltage is applied to the drain 18 of the non-volatile memory cell 2 such that electrons are deeply saturated in the region 50 of the substrate 4 adjacent the drain 18. The extent of the charge distribution in the substrate 4 during the conventional reading operation is such that the negative charge region 50 covers the portion 52 of the substrate surface 20 beneath the portion 34 of the nitride layer 10 in which the hot electrons 32 were trapped after the channel hot electron programming operation. Deep saturation of charge occurs in the substrate region 50 when the positive drain bias voltage VD is sufficiently high, such that the threshold voltage VT for allowing conduction between the drain 18 and the source 16 is no longer a sensitive function of the drain voltage VD.
A conventional reading operation is typically performed by applying a high drain voltage VD to achieve deep saturation of charge in the region 50 of the substrate 4 adjacent the drain 18 and grounding the source 16. A positive gate voltage VG is typically applied to the gate 14 of the non-volatile memory cell 2 during the conventional reading operation. Since a sufficiently large number of hot electrons 32 are trapped in the portion 34 of the nitride layer 10 adjacent the drain region 18 after a typical channel hot electron programming operation, the presence of the hot electrons 32 in the portion 34 of the nitride layer 10 can be detected without a high degree of sensitivity.
A high drain bias voltage vD applied to the drain 18 of the non-volatile memory cell 2 produces deep saturation of charge in the region 50 of the substrate 4 such that the saturated charge beneath the portion 52 of the substrate surface 20 is able to xe2x80x9ccoverxe2x80x9d the hot electrons 32 trapped in the portion 34 of the nitride layer 10 during the conventional reading operation. With a sufficiently high drain bias voltage VD, the threshold voltage VT does not vary greatly with respect to the drain voltage VD. In a typical reading operation, the high drain bias voltage VD applied to the drain 18 of the non-volatile memory cell 2 to produce deep saturation of charge in the substrate region 50 adjacent the drain 18 is typically greater than 1.6 V with a gate voltage VG of about 3.3 V applied to the gate 14 of the non-volatile memory cell 2.
After the non-volatile memory cell is programmed, it can be erased by using a conventional technique of drain side hot hole injection. Although drain side hot hole injection supposedly removes the hot electrons trapped in the portion of the nitride layer adjacent the drain region after the programming operation, some residual electrons remain in the portion of the nitride layer adjacent the drain region after the erase operation which uses the conventional drain side hot hole injection technique. A problem associated with the conventional drain side hot hole injection technique is that it results in an xe2x80x9cincomplete erasexe2x80x9d after each erase operation. Because a residual amount of negative charge remains in the portion of the nitride layer adjacent the drain region and is not completely removed after each erase operation, the residual charge accumulates in the portion of the nitride layer adjacent the drain region after a few hundred or thousand program-erase cycles.
FIG. 3 shows typical charge distributions in the substrate 4 and in the nitride layer 10 of the ONO film 6 after a typical erase operation. More specifically, FIG. 3 shows an example of charge distributions in the non-volatile memory cell 2 in which both the drain side and the source side are erased with the injection of hot holes during the erase operation. As shown in FIG. 3, most of the hot electrons in the portion 38 of the nitride layer 10 adjacent the drain 18 and in the portion 36 of the nitride layer 10 adjacent the source 16 are removed by the erase operation.
However, some residual electrons 38 remain in the portions 34 and 36 of the nitride layer after a conventional erase operation which results in an xe2x80x9cincomplete erasexe2x80x9d of the non-volatile memory cell. Because the nitride layer is an insulator, the residual charge 34 tends to remain localized in the portions 34 and 36 of the nitride layer 10 without dispersing into the center of the nitride layer 10. The center of the nitride layer 10 tends to be free of residual charge after the conventional erase operation. The hole charge distribution between the source 16 and the drain 18 in the substrate 4 tends to be minimal near the center of the substrate portion between the source 16 and the drain 18.
A problem associated with a conventional erase operation is that some electrons remain in a center portion 46 of the substrate 4 between the source 16 and the drain 18 beneath the tunnel oxide layer 8 after each program-erase cycle. Because of the problem of xe2x80x9cincomplete erasexe2x80x9d resulting from conventional erase operations, the residual negative charge in the center region 14 of the substrate 4 beneath the tunnel oxide layer 8 accumulates and grows in magnitude after a number of repeated program-erase cycles.
Depending upon the gate, source and drain voltages applied to the non-volatile memory cell 2 and the doping profiles of the source 16 and the drain 18, charge distributions other than those shown in FIG. 3 in the substrate 4 and the nitride layer 10 of the ONO film are also possible. For example, if only the drain side of the non-volatile memory cell 2 is erased with hot hole injection, only the portion 34 of the nitride layer 10 adjacent the drain 18 has a concentration of residual charge 38 after the erase operation. Furthermore, the positive charge in the substrate 4 tends to be concentrated in the region 44 of the substrate 4 adjacent the drain 18 and beneath the portion 34 of the nitride layer 10 in which the residual charge 38 remains after the erase operation.
The growing magnitude of the negative charge in the center portion 46 of the substrate 4 below the tunnel oxide layer 8 causes the threshold voltage VT for allowing conduction between the source and the drain to shift progressively positive as the number of program-erase cycles increases. The shifting of the threshold voltage VT is an undesirable feature in a non-volatile memory cell because different gate voltages would be required for erase operations depending upon the number of program-erase cycles already performed on the non-volatile memory cell.
After each erase operation, an erase-verify operation is usually performed on the non-volatile memory cell to ensure that the bit stored in the non-volatile memory cell has been erased. Erase-verify operations have been traditionally performed in the same manner as conventional reading operations. For example, as in a conventional reading operation, a high drain bias voltage is applied to the drain of the non-volatile memory cell in a conventional erase-verify operation after each program-erase cycle. The source of the non-volatile memory cell is grounded during the conventional erase-verify operation.
A disadvantage of the conventional erase-verify operation is that the high drain bias voltage applied to the drain of the non-volatile memory cell prevents the small amount of residual negative charge remaining in the portion of the nitride layer adjacent the drain after each program-erase cycle from being sensed effectively. Whereas a conventional reading operation after each programming operation can be performed with a high drain bias voltage without the need to be highly sensitive to the negative charge produced by a large number of hot electrons generated in the channel and trapped in the portion of the nitride layer adjacent the drain during the programming operation, there is a need for detecting the residual charge left over in the portion of the nitride layer adjacent the drain after each conventional erase operation with greater sensitivity.
The present invention satisfies this need. In accordance with the present invention, a method of performing an erase-verify operation on a non-volatile memory cell, which is applied a high drain voltage during a conventional reading operation, comprises the step applying a low drain voltage less than the high drain voltage to the drain of the non-volatile memory cell. In an embodiment in which the high drain voltage applied to the drain of the non-volatile memory cell during a conventional reading operation is at least 1.6 V, the low drain voltage during the erase-verify operation according to the present invention is in the range of about 0.25 V to about 1.5 V. In a further embodiment, the low drain voltage is on the order of about 0.5 V.
During the erase-verify operation with a low drain bias voltage according to the present invention, a positive gate voltage is applied to the gate of the non-volatile memory cell in dependence upon the threshold voltage VT to turn on the non-volatile memory cell, that is, to allow conduction between the source and the drain. In an embodiment, the gate voltage for the erase-verify operation according to the present invention is approximately equal to the gate voltage applied to the gate of the non-volatile memory cell during the conventional reading operation.
In an embodiment, the gate voltage applied to the gate of the non-volatile memory cell during the erase-verify operation according to the present invention is in the range of about 2 V to about 5 V. In a further embodiment, the gate voltage applied to the gate of the non-volatile memory cell during the erase-verify operation according to the present invention is on the order of about 3.3 V. The source of the non-volatile memory cell is grounded during the erase-verify operation according to the present invention.
Advantageously, the method of performing the erase-verify operation using a low drain bias voltage according to the present invention allows the residual charge remaining in the portion of the nitride layer adjacent the drain after a conventional erase operation to be sensed more effectively. Because the presence of the residual charge in the portion of the nitride layer adjacent the drain after each erase cycle is a sensitive function of drain voltage during the subsequent erase-verify operation, a low drain bias voltage allows the presence of the residual charge to be detected with greater sensitivity during the erase-verify operation according to the present invention.